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c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - a u g . , 2 0 0 8 a p w 7 0 7 4 w w w . a n p e c . c o m . t w 1 f e a t u r e s a p p l i c a t i o n s g e n e r a l d e s c r i p t i o n the apw7074 is a voltage mode synchronous pwm con- troller with fixed 300khz switching frequency, which driv- ers dual n-channel mosfets. the device integrates the controling, monitoring, and protecting functions into a single package, which provides a controlled power out- put with under-voltage and over-current protections. the apw7074 provides excellent regulation for out- put load variation. the internal 0.8v temperature-com- pensated reference voltage is designed for the require- ments of low output voltage applications. the apw7074 has excellent protection functions: por, ocp, and uvp. the power-on-reset (por) circuit can monitor the vcc, en, and ocset voltage to make sure the supply voltage exceeds their threshold voltage while the controller is running. the over-current pro- tection (ocp) monitors the output current by using the voltage drop across the upper and lower mosfet?s r ds (on) . when the output current reaches the trip point, the controller will run the soft-start function until the fault events are removed. the under-voltage protection (uvp) monitors the voltage at fb pin (v fb ) for short-circuit pro- tection when the v fb is less 50% v ref , the controller will shutdown the ic directly. g r a p h i c c a r d s p i n c o n f i g u r a t i o n s y n c h r o n o u s b u c k p w m c o n t r o l l e r single 12v power supply required 0.8v reference with 1% accuracy shutdown and soft-start function 300khz fixed switching frequency voltage mode pwm control design up to 100% duty cycle under-voltage protection over-current protection s o p - 1 4 p a c k a g e l e a d f r e e a n d g r e e n d e v i c e s a v a i l a b l e ( r o h s c o m p l i a n t ) 1 3 2 4 6 5 7 boot nc fb comp gnd en 14 12 13 11 9 10 8 ugate phase ocset lgate pgnd vcc ss sop-14 top view pvcc a n p e c r e s e r v e s t h e r i g h t t o m a k e c h a n g e s t o i m p r o v e r e l i a b i l i t y o r m a n u f a c t u r a b i l i t y w i t h o u t n o t i c e , a n d a d v i s e c u s t o m e r s t o o b t a i n t h e l a t e s t v e r s i o n o f r e l e v a n t i n f o r m a t i o n t o v e r i f y b e f o r e p l a c i n g o r d e r s .
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - a u g . , 2 0 0 8 a p w 7 0 7 4 w w w . a n p e c . c o m . t w 2 o r d e r i n g a n d m a r k i n g i n f o r m a t i o n n o t e : a n p e c l e a d - f r e e p r o d u c t s c o n t a i n m o l d i n g c o m p o u n d s / d i e a t t a c h m a t e r i a l s a n d 1 0 0 % m a t t e t i n p l a t e t e r m i n a t i o n f i n i s h ; w h i c h a r e f u l l y c o m p l i a n t w i t h r o h s . a n p e c l e a d - f r e e p r o d u c t s m e e t o r e x c e e d t h e l e a d - f r e e r e q u i r e m e n t s o f i p c / j e d e c j - s t d - 0 2 0 c f o r m s l c l a s s i f i c a t i o n a t l e a d - f r e e p e a k r e f l o w t e m p e r a t u r e . a n p e c d e f i n e s ? g r e e n ? t o m e a n l e a d - f r e e ( r o h s c o m p l i a n t ) a n d h a l o g e n f r e e ( b r o r c l d o e s n o t e x c e e d 9 0 0 p p m b y w e i g h t i n h o m o g e n e o u s m a t e r i a l a n d t o t a l o f b r a n d c l d o e s n o t e x c e e d 1 5 0 0 p p m b y w e i g h t ) . symbol parameter rating unit v cc, pvcc vcc , pvcc to gnd - 0.3 to +16 v boot boot to phase - 0.3 to +16 v ugate ugate to phase <400ns pulse width >400ns pulse width - 5 to boot+5 - 0.3 to boot +0.3 v lgate lgat e to pgnd <400ns pulse width >400ns pulse width - 5 to pvcc+5 - 0.3 to boot +0.3 v phase phase to gnd <400ns pulse width >400ns pulse width - 10 to +30 - 0.3 to 1 6 v ocset ocset to gnd vcc+0.3 v fb, comp fb, comp to gnd - 0.3 to 7 v pgnd pgnd to gnd - 0.3 to +0.3 v t j junction temperature range - 20 to +150 c t stg storage temperature - 65 ~ 150 c t sdr maximum lead soldering temperature , 10 seconds 260 c a b s o l u t e m a x i m u m r a t i n g s n o t e 1 : a b s o l u t e m a x i m u m r a t i n g s a r e t h o s e v a l u e s b e y o n d w h i c h t h e l i f e o f a d e v i c e m a y b e i m p a i r e d . e x p o s u r e t o a b s o l u t e m a x i m u m r a t i n g c o n d i t i o n s f o r e x t e n d e d p e r i o d s m a y a f f e c t d e v i c e r e l i a b i l i t y . apw7074 handling code temp erature ra nge package code assembly material apw7074 k : apw7074 xxxxx xxxxx - date code package code k : sop-14 operating ambient tem p erature ran ge e : -20 to 70 c handling code tr : tape & reel assembly material l : lead free device g : halogen and lead free device
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - a u g . , 2 0 0 8 a p w 7 0 7 4 w w w . a n p e c . c o m . t w 3 symbol parameter rating unit v cc, pvcc ic supply voltage 10.8 to 13.2 v v in converter input voltage 2.2 to 13.2 v v out converter output voltage 0.8 to 5 v i out converter output current 0 to 25 a t a ambient temperature range - 20 to 70 c t j junction temperature range - 20 to 125 c r e c o m m e n d e d o p e r a t i n g c o n d i t i o n s u n l e s s o t h e r w i s e s p e c i f i e d , t h e s e s p e c i f i c a t i o n s a p p l y o v e r v c c = 1 2 v , a n d t a = - 2 0 ~ 7 0 c . t y p i c a l v a l u e s a r e a t t a = 2 5 c . e l e c t r i c a l c h a r a c t e r i s t i c s apw70 74 symbol parameter test conditions min . typ . max . unit input supply current vcc supply current (shutdown mode) ugate, lgate and en = gnd - 0. 8 1 .6 ma i cc vcc supply current ugate and lgate o pen - 5 10 ma power - on - reset rising vcc threshol d 9 9.5 10.0 v falling vcc threshold 7.5 8 8.5 v rising v ocset threshold - 1.3 - v vocset hysteresis voltage - 0.1 - v rising en threshold voltage - 1.3 - v en hysteresis voltage - 0.1 - v oscillator f osc oscillator frequency 255 300 345 khz v osc ramp amplitude (nominal 1.35v to 2.95v) (note2) - 1 .6 - v duty duty cycle range 0 - 100 % reference v ref reference voltage - 0. 8 0 - v reference voltage tolerance - 1 - +1 %
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - a u g . , 2 0 0 8 a p w 7 0 7 4 w w w . a n p e c . c o m . t w 4 u n l e s s o t h e r w i s e s p e c i f i e d , t h e s e s p e c i f i c a t i o n s a p p l y o v e r v c c = 1 2 v , a n d t a = - 2 0 ~ 7 0 c . t y p i c a l v a l u e s a r e a t t a = 2 5 c . e l e c t r i c a l c h a r a c t e r i s t i c s ( c o n t . ) apw70 74 symbol parameter test conditions min . typ . max . unit pwm e rr or amplifier gain open loop gain r l = 10k, c l = 10p f (note2) - 88 - db gbwp open loop bandwidth r l = 10k, c l = 10p f (note2) - 15 - mhz sr slew rate r l = 10k, c l = 10p f (note2) - 6 - v/ m s fb input current v fb = 0.8v - 0.1 1 m a v copm comp high voltage - 5.5 - v v copm comp low voltage - 0 - v i comp comp source current v comp = 2v - 5 - ma i comp comp sink current v comp = 2v - 5 - ma gate drivers i ugate upper gate source current boo t = 12 v, v ugate - v phase = 2 v - 2.6 - a i ugate upper gate s ink current boot = 12 v, v ugate - v phase = 2 v - 1.05 - a i l gate low er gate source current pvcc = 12 v, v l gate = 2 v - 4.9 - a i lgate low er gate s ink current pvcc = 12 v, v l gate = 2 v - 1.4 - a r ugate upper gate s ource impedance boot = 12v, i ugate = 0. 1 a - 2 3 w r ugate upper gate sink impedance boot = 12v, i ugate = 0. 1 a - 1.6 2.4 w r l gate low er gate source impedance pvcc = 12v, i l gate = 0. 1 a - 1.3 1.95 w r lgate lower gate sink impedance pvcc = 12v, i l gate = 0. 1 a - 1.25 1.8 8 w t d dead time - 20 - ns protection uv fb fb under voltage level percent of v ref 45 50 55 % i ocset ocset source current (hi - side) v ocset = 11 .5v 170 200 2 5 0 m a v ocp ocp voltage (low - side) 270 2 9 0 310 mv soft - start i ss sof t - star t charge current 8 10 12 m a note 2:guaranteed by design.
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - a u g . , 2 0 0 8 a p w 7 0 7 4 w w w . a n p e c . c o m . t w 5 t y p i c a l a p p l i c a t i o n c i r c u i t vcc boot ugate phase pvcc lgate pgnd gnd ocset fb ss en v out 12v v in on off comp 2.37k 1nf 0.1 m f apm2509 apm2506 1 m f 22nf 1 m f scd24 1n4148 1 m h 470 m f 2.2 m h 470 m fx2 1000 m fx2 2k 1k 1.5nf 7.5r 18r 68nf 8.2nf 33nf 2.7k
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - a u g . , 2 0 0 8 a p w 7 0 7 4 w w w . a n p e c . c o m . t w 6 b l o c k d i a g r a m gate control oscillator soft - start power- on - reset phase lgate fb ss gnd en vcc ocset boot ugate pgnd pvcc i ocset 200 m a i ss 10 m a 50%v ref o.c.p comparator error amp pwm comparator u.v.p comparator sawtooth wave : 2 comp 0.29v o.c.p comparator v ref f osc 300 k h z v cc
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - a u g . , 2 0 0 8 a p w 7 0 7 4 w w w . a n p e c . c o m . t w 7 f u n c t i o n p i n d e s c r i p t i o n v c c ( p i n 1 4 ) p o w e r s u p p l y i n p u t p i n . c o n n e c t a n o m i n a l 1 2 v p o w e r s u p p l y t o t h i s p i n . t h i s p i n a l s o h a s a p o w e r - o n - r e s e t f u n c t i o n , w h i c h m o n i t o r s t h e i n p u t v o l t a g e . i t i s r e c o m m e n d e d t h a t a d e c o u p l i n g c a p a c i t o r ( 1 t o 1 0 m f ) b e c o n n e c t e d t o g n d f o r n o i s e d e c o u p l i n g . p v c c ( p i n 1 3 ) t h i s p i n p r o v i d e s a s u p p l y v o l t a g e f o r t h e l o w e r g a t e d r i v e . c o n n e c t t h i s p i n t o v c c p i n i n n o r m a l u s e . b o o t ( p i n 1 0 ) t h i s p i n p r o v i d e s t h e b o o t s t r a p v o l t a g e t o t h e u p p e r g a t e d r i v e r i n o r d e r t o d r i v e t h e n - c h a n n e l m o s f e t . p h a s e ( p i n 8 ) t h i s p i n i s t h e r e t u r n p a t h f o r t h e u p p e r g a t e d r i v e r . c o n - n e c t t h i s p i n t o t h e u p p e r m o s f e t s o u r c e . t h i s p i n i s a l s o u s e d t o m o n i t o r t h e v o l t a g e d r o p a c r o s s t h e m o s f e t f o r o v e r - c u r r e n t p r o t e c t i o n . g n d ( p i n 7 ) t h i s p i n i s t h e s i g n a l g r o u n d p i n . c o n n e c t t h e g n d p i n t o a g o o d g r o u n d p l a n e . p g n d ( p i n 1 1 ) t h i s p i n i s t h e p o w e r g r o u n d p i n f o r t h e l o w e r g a t e d r i v e r . i t s h o u l d b e t i e d t o t h e g n d p i n o n t h e b o a r d . c o m p ( p i n 4 ) t h i s p i n i s t h e o u t p u t o f p w m e r r o r a m p l i f i e r . i t i s u s e d t o s e t t h e c o m p e n s a t i o n c o m p o n e n t s . f b ( p i n 5 ) t h i s p i n i s t h e i n v e r t i n g i n p u t o f t h e p w m e r r o r a m p l i f i e r . i t i s u s e d t o s e t t h e o u t p u t v o l t a g e a n d t h e c o m p e n s a t i o n c o m p o n e n t s . t h i s p i n i s a l s o m o n i t o r e d f o r u n d e r - v o l t a g e p r o t e c t i o n . i f t h e f b v o l t a g e i s u n d e r 5 0 % o f t h e r e f e r e n c e v o l t a g e , t h e d e v i c e w i l l b e s h u t d o w n . u g a t e ( p i n 9 ) t h i s p i n i s t h e g a t e d r i v e r f o r t h e u p p e r m o s f e t o f p w m o u t p u t . l g a t e ( p i n 1 2 ) t h i s p i n i s t h e g a t e d r i v e r f o r t h e l o w e r m o s f e t o f p w m o u t p u t . s s ( p i n 3 ) c o n n e c t a c a p a c i t o r t o g n d a n d a 1 0 m a c u r r e n t s o u r c e c h a r g e s t h i s c a p a c i t o r t o s e t t h e s o f t - s t a r t t i m e . o c s e t ( p i n 2 ) t h i s p i n s e r v e s t w o f u n c t i o n s : a s h u t d o w n c o n t r o l a n d t h e s e t t i n g o f o v e r c u r r e n t l i m i t t h r e s h o l d . p u l l i n g t h i s p i n b e l o w 1 . 3 v w i l l s h u t d o w n t h e c o n t r o l l e r , f o r c i n g t h e u g a t e a n d l g a t e s i g n a l s t o b e l o w . a r e s i s t o r ( r o c s e t ) c o n n e c t e d b e t w e e n t h i s p i n a n d t h e d r a i n o f t h e h i g h s i d e m o s f e t w i l l d e t e r m i n e t h e o v e r c u r r e n t l i m i t . a n i n t e r n a l 2 0 0 m a c u r r e n t s o u r c e w i l l f l o w t h r o u g h t h i s r e s i s t o r , c r e a t i n g a v o l t a g e d r o p , w h i c h w i l l b e c o m p a r e d w i t h t h e v o l t a g e a c r o s s t h e h i g h s i d e m o s f e t . t h e t h r e s h o l d o f t h e o v e r c u r r e n t l i m i t i s t h e r e - f o r e g i v e n b y : ( ) ds(on) ocset ocset peak r r 200ua i i = e n ( p i n 6 ) p u l l t h i s p i n a b o v e 1 . 3 v t o e n a b l e t h e d e v i c e a n d b e l o w 1 . 2 v t o d i s a b l e t h e d e v i c e . i n s h u t d o w n , t h e s s i s d i s - c h a r g e d a n d t h e u g a t e a n d l g a t e p i n s a r e h e l d l o w . n o t e t h a t d o n ? t l e a v e t h i s p i n o p e n .
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - a u g . , 2 0 0 8 a p w 7 0 7 4 w w w . a n p e c . c o m . t w 8 t y p i c a l o p e r a t i n g c h a r a c t e r i s t i c s p o w e r o n p o w e r o f f e n ( e n = v c c ) s h u t d o w n ( e n = g n d ) ch1: vcc (5v/div) ch2: ss (2v/div) ch3: vo (1v/div) time: 10ms/div ch1: vcc (5v/div) ch2: ss (2v/div) ch3: vo (1v/div) time: 2ms/div ch1 ch2 ch3 ch1 ch2 ch3 ch1 ch2 ch3 ch1 ch2 ch3 ch1: en (5v/div) ch2: ss (5v/div) ch3: vo (1v/div) time: 10ms/div ch1: en (5v/div) ch2: ss (5v/div) ch3: vo (1v/div) time: 10ms/div vcc=12v, vin =12v vo=1.5v, l=1uh vcc=12v, vin =12v vo=1.5v, l=1uh vcc=12v, vin =12v vo=1.5v, l=1uh vcc=12v, vin =12v vo=1.5v, l=1uh
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - a u g . , 2 0 0 8 a p w 7 0 7 4 w w w . a n p e c . c o m . t w 9 t y p i c a l o p e r a t i n g c h a r a c t e r i s t i c s ( c o n t . ) u g a t e r i s i n g u g a t e f a l l i n g l o a d t r a n s i e n t r e s p o n s e u n d e r v o l t a g e p r o t e c t i o n ch1 ch2 ch3 ch1 ch2 ch3 ch1 ch2 ch1 ch2 ch3 ch4 ch1: ug (20v/div) ch2: lg (5v/div) ch3: phase (10v/div) time: 50ns/div vcc=12v, vin =12v vo=1.5v, l=1uh vcc=12v, vin =12v vo=1.5v, l=1uh vcc=12v, vin =12v vo=1.5v, l=1uh vcc=12v, vin =12v vo=1.5v, l=1uh ch1: ug (20v/div) ch2: lg (5v/div) ch3: phase (10v/div) time: 50ns/div ch1: vo (500mv/div, ac) ch2:io (5a/div) time: 200us/div ch1: ss (5v/div) ch2: io (5a/div) ch3: vo (1v/div) ch4: ug (10v/div) time: 50us/div
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - a u g . , 2 0 0 8 a p w 7 0 7 4 w w w . a n p e c . c o m . t w 1 0 0.792 0.794 0.796 0.798 0.8 0.802 0.804 -40 -20 0 20 40 60 80 100 120 275 280 285 290 295 300 305 310 -40 -20 0 20 40 60 80 100 120 t y p i c a l o p e r a t i n g c h a r a c t e r i s t i c s ( c o n t . ) o v e r c u r r e n t p r o t e c t i o n s h o r t t e s t s w i t c h i n g f r e q u e n c y v s . j u n c t i o n t e m p e r a t u r e r e f e r e n c e v o l t a g e v s . j u n c t i o n t e m p e r a t u r e ch1 ch2 ch3 ch1 ch2 ch3 ch4 ch1: ss (5v/div) ch2: il (10a/div) ch3: vo (1v/div) ch4:ug (20v/div) time: 10ms/div ch1: ss (5v/div) ch2: il (10a/div) ch3: vo (1v/div) ch4:ug (20v/div) time: 10ms/div vcc =12v, vin =12v,vo=1.5v, l=1uh rocset =1k [ , rds(on )=8m [ vcc =12v, vin =12v vo=1.5v, l=1uh ch4 junction temperature ( c ) switching frequency(khz) reference voltage(v) junction temperature ( c )
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - a u g . , 2 0 0 8 a p w 7 0 7 4 w w w . a n p e c . c o m . t w 1 1 0 1 2 3 4 5 6 0 2 4 6 8 10 12 0 0.5 1 1.5 2 2.5 3 3.5 0 2 4 6 8 10 12 0 0.5 1 1.5 2 2.5 3 3.5 0 2 4 6 8 10 12 0 0.5 1 1.5 2 2.5 3 0 2 4 6 8 10 12 t y p i c a l o p e r a t i n g c h a r a c t e r i s t i c s ( c o n t . ) u g a t e s o u r c e c u r r e n t v s . u g a t e v o l t a g e u g a t e s i n k c u r r e n t v s . u g a t e v o l t a g e l g a t e s o u r c e c u r r e n t v s . l g a t e v o l t a g e l g a t e s i n k c u r r e n t v s . l g a t e v o l t a g e l g a t e v o l t a g e ( v ) lgate source current (a) lgate sink current (a) l g a t e v o l t a g e ( v ) u g a t e v o l t a g e ( v ) ugate source current (a) u g a t e v o l t a g e ( v ) ugate sink current (a) vboot=12v vboot=12v pvcc=12v pvcc=12v
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - a u g . , 2 0 0 8 a p w 7 0 7 4 w w w . a n p e c . c o m . t w 1 2 power-on-reset (por) the power-on-reset (por) function of apw7074 con- tinually monitors the input supply voltage (vcc), the en- able (en) pin, and ocset pin. the supply voltage (vcc) must exceed its rising por threshold voltage. the voltage at ocset pin is equal to v in minus a fixed voltage drop (vocset = v in - v rocset ). en pin can be pulled high with connecting a resistor to vcc. the por function initiates soft-start operation after v cc , en, and ocset voltages exceed their por thresholds. for operation with a single +12v power source, v in and vcc are equivalent and the +12v power source must exceed the rising vcc threshold. the por function inhibits operation at dis- abled status (en pin low). with both input supplies above their por thresholds, the device initiates a soft-start interval. soft-start/en the ss/en pins control the soft-start and enable or dis- able the controller. connect a soft-start capacitor from ss pin to gnd to set the soft-start interval. figure1. shows the soft-start interval. when vcc reaches its power-on-re- set threshold (9.5v), internal 10 m a current source starts to charge the capacitor. when the ss reaches the enabled threshold about 1.8v, the internal 0.8v reference starts to rise and follows the ss; the error amplifier output (comp) suddenly raises to 1.35v , which is the valley of the triangle wave of the oscillator, leads the v out to start up. until the ss reaches about 4.2v, the internal refer- ence completes the soft-start interval and reaches to 0. 8v; then v out is in regulation. the ss still rises to 5.5v and then stops. f u n c t i o n d e s c r i p t i o n v 4 . 2 i c t t t ss ss 1 2 start soft = - = - where: c ss = external soft-start capacitor i ss = soft-start current=10 m a 4.2v 1.8v t 1 t 2 t 0 voltage time v out v ss figure 1. soft-start internal over-current protection (monitor upper mosfet) the apw7074 provides two manners to protect the con- verter from abnormal output load; one monitors the voltage across the upper mosfet and uses the ocset pin to set the over-current trip point, the other monitors the voltage across the lower mosfet by comparing with an internal reference voltage (0.29v). a resistor (r ocset ) connected between ocset pin and the drain of the upper mosfet will determine the over current limit. an internal 200 m a current source will flow through this resistor, creating a voltage drop, which will be compared with the voltage across the upper mosfet. when the voltage across the upper mosfet exceeds the voltage drop across the r ocset , an over-current will be detected. the threshold of the over current limit is there- fore given by: ( ) on ds ocset ocset limit r r i i = the over-current never occurs in the normal operating load range; the variation of all parameters in the above equation should be determined. - the mosfet? r ds(on) is varied by the temperature and the gate to source voltage, the user should determine the maximum r ds(on) in manufacturer?s datasheet.
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - a u g . , 2 0 0 8 a p w 7 0 7 4 w w w . a n p e c . c o m . t w 1 3 f u n c t i o n d e s c r i p t i o n ( c o n t . ) over-current protection (cont.) - the minimum i ocset (170 m a) and minimum r ocset should be used in the above equation. - note that the i limit is the current flow through the upper mosfet; i limit must be greater than maximum out- put current add the half of inductor ripple current. an over current condition will shut down the device and discharge the c ss with a 10 m a sink current and then ini- tiate the soft-start sequence. if the over current condition is not removed during the soft-start interval, the device will be shut down while the over current is detected and the ss still rises to 4v to complete its cycle. the soft-start function will be cycled until the over-current condition is removed. both over-current protections have the same behavior while an over current condition is detected. ds(on) limit r 0.29v i = for the over-current is never occurred in the normal oper- ating load range; the parameters r ds(on) and i limit in the above equation also have the same notices as the previ- ous section. under voltage protection the fb pin is monitored during converter operation by their own under voltage (uv) comparator. if the fb volt- age drops below 50% of the reference voltage (50% of 0. 8v = 0.4v), a fault signal is internally generated, and the device turns off both high-side and low-side mosfet and the converter?s output is latched to float. over-current protection (monitor lower mosfet) the other over-current protection monitors the output cur- rent by using the voltage drop across the lower mosfet?s r ds(on) and this voltage drop will be compared with the internal 0.29v reference voltage. if the voltage drop across the lower mosfet?s r ds(on) is larger than 0.29v, an over- current condition is detected. the threshold of the over current limit is given by:
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - a u g . , 2 0 0 8 a p w 7 0 7 4 w w w . a n p e c . c o m . t w 1 4 a p p l i c a t i o n i n f o r m a t i o n output voltage selection the output voltage can be programmed with a resistive divider. the use of 1% or better resistors for the resistive divider is recommended. the fb pin is the inverter input of the error amplifier , and the reference voltage is 0.8v . the output voltage is determined by: ? ? ? ? ? + = gnd out out r r 1 0.8 v where r out is the resistor connected from v out to fb and r gnd is the resistor connected from fb to gnd. output inductor selection the inductor value determines the inductor ripple cur- rent and affects the load transient response. higher in- ductor value reduces the inductor?s ripple current and induces lower output ripple voltage. the ripple current and the ripple voltage can be approximated by: in out s out in ripple v v l f v v i - = esr i v ripple out = d where f s is the switching frequency of the regulator. although the increase of the inductor value and frequency reduces the ripple current and voltage, there is a tradeoff between the inductor?s ripple current and the regula- tor load transient response time. a smaller inductor will give the regulator a faster load transient response at the expense of higher ripple current. increasing the switching frequency (f s ) also reduces the ripple current and voltage, but it will increase the switch- ing loss of the mosfet and the power dissipation of the converter. the maximum ripple current occurs at the maximum input voltage. a good starting point is to choose the ripple current to be approximately 30% of the maximum output current. once the inductance value has been chosen, select an inductor that is capable of carrying the required peak current without going into saturation. in some types of inductors, especially those with ferrite core, the ripple current will increase abruptly when it saturates. this will result in a larger output ripple voltage. output capacitor selection higher capacitor value and lower esr reduce the out- put ripple and the load transient drop. therefore, select- ing high performance low esr capacitors is intended for switching regulator applications. in some applications, multiple capacitors have to be parallel to achieve the de- sired esr value. a small decoupling capacitor in parallel for bypassing the noise is also recommended, and the voltage rating of the output capacitors also must be considered. if tantalum capacitors are used, make sure they are surge tested by the manufactures. if in doubt, consult the capacitors manufacturer. input capacitor selection the input capacitor is chosen based on the voltage rat- ing and the rms current rating. for reliable operation, select the capacitor voltage rating to be at least 1.3 times higher than the maximum input voltage. the maximum rms current rating requirement is approximately i out / 2, where i out is the load current. during power up, the input capacitors have to handle large amount of surge current. if tantalum capacitors are used, make sure they are surge tested by the manufactures. if in doubt, consult the capacitors manufacturer. for high frequency decoupling, a ceramic capacitor 1 m f can connect between the drain of upper mosfet and the source of lower mosfet. mosfet selection the selection of the n-channel power mosfets are de- termined by the r ds(on) , reverse transfer capacitance (c rss ) and maximum output current requirement. there are two components of loss in the mosfets: conduction loss and transition loss. for the upper and lower mosfet, the losses are approximately given by the fol- lowing equations: p upper = i out 2 (1+ tc)(r ds(on) )d + (0.5)( i out )(v in )( t sw )f s p lower = i out 2 (1+ tc)(r ds(on) )(1-d) where i out is the load current tc is the temperature dependency of r ds(on) f s is the switching frequency t sw is the switching interval d is the duty cycle
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - a u g . , 2 0 0 8 a p w 7 0 7 4 w w w . a n p e c . c o m . t w 1 5 a p p l i c a t i o n i n f o r m a t i o n ( c o n t . ) mosfet selection (cont.) note that both mosfets have conduction loss while the upper mosfet include an additional transition loss. the switching internal, t sw , is the function of the reverse trans- fer capacitance c rss . the (1+tc) term is to factor in the temperature dependency of the r ds(on) and can be ex- tracted from the ?r ds(on) vs tempera ture? curve of the power mosfet. pwm compensation the output lc filter of a step down converter introduces a double pole, which contributes to -40db/decade gain slope and 180 degrees phase shift in the control loop. a compensation network among comp, fb, and v out should be added. the compensation network is shown in fig. 5. the output lc filter consists of the output induc- tor and output capacitors. the transfer function of the lc filter is given by: 1 c esr s c l s c esr s 1 gain out out 2 out lc + + + = the poles and zero of this transfer functions are: out lc c l 2 1 f p = out esr c esr 2 1 f p = the f lc is the double poles of the lc filter, and f esr is the zero introduced by the esr of the output capacitor. phase l output c out esr figure 2. the output lc filter f lc f esr -40db/dec -20db/dec frequency(hz) gain (db) figure 3. the lc filter gain and frequency the pwm modulator is shown in figure 4. the input is the output of the error amplifier and the output is the phase node. the transfer function of the pwm modu- lator is given by: figure 4. the pwm modulator output of error amplifier g v osc pwm comparator driver driver phase v in osc the compensation network is shown in figure 5. it provides a close loop transfer function with the highest zero crossover frequency and sufficient phase margin. the transfer function of error amplifier is given by: osc in pwm v v gain d = ? ? ? ? + ? ? ? ? + = = sc3 1 r3 r1// sc2 1 r2 // sc1 1 v v gain out comp amp ( ) ? ? ? ? + ? ? ? ? + + ? ? ? ? ? + + ? ? ? ? + + = c3 r3 1 s c2 c1 r2 c2 c1 s s c3 r3 r1 1 s c2 r2 1 s c1 r3 r1 r3 r1
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - a u g . , 2 0 0 8 a p w 7 0 7 4 w w w . a n p e c . c o m . t w 1 6 a p p l i c a t i o n i n f o r m a t i o n ( c o n t . ) the poles and zeros of the transfer function are: c2 r2 2 1 f z1 p = ( ) c3 r3 r1 2 1 f z2 + p = ? ? ? ? + p = c2 c1 c2 c1 r2 2 1 f p1 c3 r3 2 1 f p2 p = pwm compensation (cont.) the closed loop gain of the converter can be written as: gain lc x gain pwm x gain amp figure 6. shows the asymptotic plot of the closed loop converter gain, and the following guidelines will help to design the compensation network. using the below guidelines should give a compensation similar to the curve plotted. a stable closed loop has a -20db/ decade slope and a phase margin greater than 45 degree. 1.choose a value for r1, usually between 1k and 5k. 2.select the desired zero crossover frequency f o : (1/5 ~ 1/10) x f s >f o >f esr use the following equation to calculate r2: v ref v out v comp r 1 r 3 c 3 r 2 c 2 c 1 fb figure 5. compensation network 3.place the first zero f z1 before the output lc filter double pole frequency f lc . f z1 = 0.75 x f lc calculate the c2 by the equation: 0.75 f r2 2 1 c2 lc p = 4.set the pole at the esr zero frequency f esr : f p1 = f esr calculate the c1 by the equation: 1 f c2 r2 2 c2 c1 esr - p = r1 f f v v r2 lc o in osc d = 5.set the second pole f p2 at the half of the switching fre- quency and also set the second zero f z2 at the output lc filter double pole f lc . the compensation gain should not exceed the error amplifier open loop gain, check the compensation gain at f p2 with the capabilities of the error amplifier. f p2 = 0.5 x f s f z2 = f lc combine the two equations will get the following com- ponent calculations: 1 f 2 f r1 r3 lc s - = s f r3 1 c3 p = f lc frequency(hz) g a i n ( d b ) 20log (r2/r1) 20log (v in / g v osc ) f z1 f z2 f p1 f p2 f esr pwm & filter gain converter gain compensation gain figure 6. converter gain and frequency
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - a u g . , 2 0 0 8 a p w 7 0 7 4 w w w . a n p e c . c o m . t w 1 7 a p p l i c a t i o n i n f o r m a t i o n ( c o n t . ) layout consideration in any high switching frequency converter, a correct lay- out is important to ensure proper operation of the regulator. with power devices switching at 300khz,the resulting current transient will cause voltage spike across the interconnecting impedance and parasitic circuit elements. as an example, consider the turn-off transition of the pwm mosfet. before turn-off, the mosfet is car- rying a full load current. during turn-off, current stops flowing in the mosfet and is free-wheeling by the lower mosfet and parasitic diode. any parasitic inductance of the circuit generates a large voltage spike during the switching interval. in general, using short and wide printed circuit traces should minimize interconnecting im- pedances and the magnitude of voltage spike. also, sig- nal and power grounds are to be kept separate till com- bined using ground plane construction or single point grounding. figure 7. illustrates the layout, with bold lines indicating high current paths; these traces must be short and wide. components along the bold lines should be placed closely together. below is a checklist for your layout: - keep the switching nodes (ugate, lgate, and phase) away from sensitive small signal nodes since these nodes are fast moving signals. therefore, keep traces to these nodes as short as possible. - the traces from the gate drivers to the mosfets (ug and lg) should be short and wide. - place the source of the high-side mosfet and the drain of the low-side mosfet as close as possible. minimizing the impedance with wide layout plane between the two pads reduces the voltage bounce of the node. - decoupling capacitor, compensation component, the resistor dividers, boot capacitors, and ss ca - pacitors should be close their pins. (for example, place the decoupling ceramic capacitor near the drain of the high-side mosfet as close as possible. the bulk capacitors are also placed near the drain). vcc pvcc boot phase ugate lgate v in v out l o a d apw7074 figure 7.layout guidelines - the input capacitor should be near the drain of the upper mosfet; the output capacitor should be near the loads. the input capacitor gnd should be close to the output capacitor gnd and the lower mosfet gnd. - the drain of the mosfets (v in and phase nodes) should be a large plane for heat sinking.
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - a u g . , 2 0 0 8 a p w 7 0 7 4 w w w . a n p e c . c o m . t w 1 8 p a c k a g e i n f o r m a t i o n s o p ? 1 4 s y m b o l min. max. 1.75 0.10 0.17 0.25 0.25 a a1 c d e e1 e h l millimeters b 0.31 0.51 sop-14 0.25 0.50 0.40 1.27 min. max. inches 0.069 0.004 0.012 0.020 0.007 0.010 0.010 0.020 0.016 0.050 0 0.010 1.27 bsc 0.050 bsc a2 1.25 0.049 0 8 0 8 l view a 0 . 2 5 seating plane gauge plane note: 1. follow jedec ms-012 ab. 2. dimension ? d ? does not include mold flash, protrusions or gate burrs. mold flash, protrusion or gate burrs shall not exceed 6 mil per side. 3. dimension ? e ? does not include inter-lead flash or protrusions. inter-lead flash and protrusions shall not exceed 10 mil per side. 3.80 5.80 8.55 4.00 6.20 8.75 0.337 0.344 0.228 0.244 0.150 0.157 d e b e 1 e see view a c h x 4 5 a a 1 a 2
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - a u g . , 2 0 0 8 a p w 7 0 7 4 w w w . a n p e c . c o m . t w 1 9 application a h t1 c d d w e1 f 330.0 ? 2.00 50 min. 16.4+2.00 - 0.00 13.0+0.50 - 0.20 1.5 min. 20.2 min. 16.0 ? 0.30 1.75 ? 0.10 7.50 ? 0.10 p 0 p1 p 2 d 0 d1 t a 0 b 0 k 0 sop - 14 4.0 ? 0.10 8.0 ? 0.10 2.0 ? 0.10 1.5+0.10 - 0.00 1.5 min. 0.6+0.00 - 0. 40 6.40 ? 0.20 9.00 ? 0.20 2.10 ? 0.20 (mm) c o v e r t a p e d i m e n s i o n s package type unit quantity so p - 14 tape & reel 2500 c a r r i e r t a p e & r e e l d i m e n s i o n s h t1 a d a e 1 a b w f t p0 od0 b a0 p2 k0 b 0 section b-b section a-a od1 p1
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - a u g . , 2 0 0 8 a p w 7 0 7 4 w w w . a n p e c . c o m . t w 2 0 r e f l o w c o n d i t i o n ( i r / c o n v e c t i o n o r v p r r e f l o w ) test item method description solderability mil - std - 883d - 2003 245 c, 5 sec holt mil - std - 883d - 1005.7 1000 hrs bias @125 c pct jesd - 22 - b, a102 168 hrs, 100 % rh, 121 c tst mil - std - 883d - 1011.9 - 65 c~150 c, 200 cycles esd mil - std - 883d - 3015.7 vhbm > 2kv, vmm > 200v latch - up jesd 78 10ms, 1 tr > 100ma r e l i a b i l i t y t e s t p r o g r a m t 25 c to peak tp ramp-up t l ramp-down ts preheat tsmax tsmin t l t p 25 t e m p e r a t u r e time critical zone t l to t p t a p i n g d i r e c t i o n i n f o r m a t i o n sop-14 user direction of feed
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - a u g . , 2 0 0 8 a p w 7 0 7 4 w w w . a n p e c . c o m . t w 2 1 table 2. pb - free process ? package classification reflow temperatures package thickness volume mm 3 <350 volume mm 3 350 - 2000 volume mm 3 >2000 <1.6 mm 260 +0 c* 260 +0 c* 260 +0 c* 1.6 mm ? 2.5 mm 260 +0 c* 250 +0 c* 245 +0 c* 3 2.5 mm 250 +0 c* 245 +0 c* 245 +0 c* *tolerance: the device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means peak reflow temperature +0 c. for example 260 c+0 c) at the rated msl level. table 1. snpb eutectic process ? package peak reflow temperature s package thickness volume mm 3 <350 volume mm 3 3 350 <2.5 mm 240 +0/ - 5 c 225 +0/ - 5 c 3 2.5 mm 225 +0/ - 5 c 225 +0/ - 5 c c u s t o m e r s e r v i c e a n p e c e l e c t r o n i c s c o r p . head office : no.6, dusing 1st road, sbip, hsin-chu, taiwan tel : 886-3-5642000 fax : 886-3-5642050 t a i p e i b r a n c h : 2 f , n o . 1 1 , l a n e 2 1 8 , s e c 2 j h o n g s i n g r d . , s i n d i a n c i t y , t a i p e i c o u n t y 2 3 1 4 6 , t a i w a n t e l : 8 8 6 - 2 - 2 9 1 0 - 3 8 3 8 f a x : 8 8 6 - 2 - 2 9 1 7 - 3 8 3 8 c l a s s i f i c a t i o n r e f l o w p r o f i l e s profile feature sn - pb eutectic assembly pb - free assembly average ramp - up rate (t l to t p ) 3 c/second max. 3 c/second max. preheat - temperature min (tsmin) - temperature max (tsmax) - time (min to max) (ts) 100 c 150 c 60 - 120 seconds 150 c 200 c 60 - 180 seconds time maintained above: - temperature (t l ) - time (t l ) 183 c 60 - 150 seconds 217 c 60 - 150 seconds peak /classification temperature (tp) see table 1 see table 2 time within 5 c of actual peak temperature (tp) 10 - 30 seconds 20 - 40 seconds ramp - down rate 6 c/sec ond max. 6 c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. notes: all temperatures refer to topside of the package. measured on the body surface.

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